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Receiver Skew Margin for Non-DPA Mode
SV51007
2014.01.10
Conventions used for the equation:
? RSKM — the timing margin between the receiver ’ s clock input and the data input sampling window.
? Time unit interval (TUI) — time period of the serial data.
? SW — the period of time that the input data must be stable to ensure that data is successfully sampled by
the LVDS receiver. The SW is a device property and varies with device speed grade.
? TCCS — the timing difference between the fastest and the slowest output edges, including t CO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement.
You must calculate the RSKM value to decide whether the LVDS receiver can sample the data properly or
not, given the data rate and device. A positive RSKM value indicates that the LVDS receiver can sample the
data properly, whereas a negative RSKM indicates that it cannot sample the data properly.
The following figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.
Figure 6-31: Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal
Clock
TCCS
TCCS
Receiver
Input Data
Timing Budget
RSKM
t SW (min)
Bit n
SW
Internal
Clock
Falling Edge
t SW (max)
Bit n
RSKM
TUI
External
Clock
Clock Placement
Internal
Clock
Synchronization
Transmitter
Output Data
TCCS
RSKM
RSKM
TCCS
2
Receiver
Input Data
SW
For LVDS receivers, the Quartus II software provides an RSKM report showing the SW, TUI, and RSKM
values for non-DPA LVDS mode:
? You can generate the RSKM report by executing the report_RSKM command in the TimeQuest Timing
Analyzer. You can find the RSKM report in the Quartus II compilation report in the TimeQuest Timing
Analyzer section.
? To obtain the RSKM value, assign the input delay to the LVDS receiver through the constraints menu of
the TimeQuest Timing Analyzer. The input delay is determined according to the data arrival time at the
LVDS receiver port, with respect to the reference clock.
? If you set the input delay in the settings parameters for the Set Input Delay option, set the clock name
to the clock that reference the source synchronous clock that feeds the LVDS receiver.
Altera Corporation
High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
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